The present invention relates to microprocessors, and in particular, to an apparatus and a method for variable size pages using fixed size translation lookaside buffer entries.
Microprocessors typically implement a paging system. For example, the well known Intel X86(trademark) and Intel Pentium(trademark) microprocessors each implement a paging system for fixed size pages. In particular, the Intel Pentium(trademark) microprocessor implements a paging system that provides two fixed-size pages: a 4 K (Kilobyte) page, and a 4 M (Megabyte) page.
Generally, a paging system uses a page directory and a page table to map a linear (or virtual) address to a physical address (i.e., a physical memory address). If a segmentation system is also implemented, then a segment translator is typically provided, which translates a linear address to a linear address and passes the linear address to the paging system (e.g., page translator). For example, in the Intel X86(trademark) microprocessor architecture, a 32-bit linear address includes a 10-bit index into a page directory, a 10-bit index into a page table, and a 12-bit offset within a page. In particular, two levels of page tables are used. The top level page table is called the page directory, which maps the upper 10 bits of the 32-bit linear address to the second level of page tables. The second level of page tables maps the middle 10 bits of the 32-bit linear address to the base address of a page in physical memory (also called a page frame address). The lower 12 bits of the 32-bit linear address represent a 12-bit offset within the page addressed by the page table. Accordingly, the 32-bit linear address is translated into a 32-bit physical address.
Because the translation of a linear address to a physical address can require two additional memory accesses, a microprocessor typically includes a special cache called a TLB (Translation Lookaside Buffer). For example, the Intel X86(trademark) and Intel Pentium(trademark) microprocessors each include a TLB. Generally, the TLB can satisfy many of the requests for reading the page tables. Thus, in the Intel Pentium(trademark) and Intel Pentium Pro(trademark) microprocessor architecture, a TLB for storing entries for 4 K pages and a TLB for storing entries for 4 M pages are both provided.
Accordingly, the present invention provides an apparatus and a method for variable size pages using fixed size TLB (Translation Lookaside Buffer) entries. In particular, the apparatus and the method of the present invention provide an enhanced and cost-effective paging system with improved performance.
In one embodiment, an apparatus for variable size pages using fixed TLB entries includes a first TLB for fixed size pages and a second TLB for variable size pages. In particular, the second TLB stores fixed size TLB entries for variable size pages while maintaining compatibility with the industry-prevalent Intel x86(trademark)/Pentium(trademark) fixed size TLB entries. In a preferred embodiment, the first TLB stores entries for 4 K (Kilobyte) pages, and the second buffer stores fixed 4 M TLB entries for 4 K to 4 M (Megabyte) pages (in 4 K increments aligned at 2n * 4 K physical boundaries).
In this embodiment, an Operating System software (OS) ensures that the following conditions are satisfied: (1) all memory blocks are aligned on a 4 M linear address boundary so that the lower 22 bits of the starting linear address of the memory block are zero; (2) no two such memory blocks are mapped in the same 4 M linear address range; (3) there are no overlapping mappings for the addresses in the first TLB and the second TLB; and (4) the memory block is correctly size-aligned in physical memory go that the lower log2(least 2n greater than =memory-block-size) offset bits start out as zero. As a result, during the translation of the linear address to the physical address, OR""ing the upper offset of a linear address, which represents the upper 10 bits of the 10+12 bit page offset, with the lower offset of an entry in the second TLB, which represents the lower 10 bits of a 20-bit physical page frame number, generates the middle 10 bits of a physical address (e.g., bits 21:12 of a 32-bit physical address). The upper 10 bits of the 20-bit physical page frame number and the lower 12 bits of the linear address (i.e., the page offset) are then concatenated with the OR""d bits to form the translated physical address.
Accordingly, this embodiment provides a cost-effective and enhanced paging system that implements variable size pages using fixed 4 M TLP entries. Moreover, the apparatus in accordance with this embodiment of the present invention uses a logical OR operation instead of an arithmetic add operation to improve performance during the translation of a linear address to a physical address.
In another embodiment, the fourth condition is not required, and an adder (instead of an OR device) is used to translate a linear address to a physical address. Alternatively, a hardware implementation can use an adder per 4 M TLB entry to compute addresses in parallel with a TLB lookup.
In one embodiment, a method for variable size pages using fixed size TLB entries includes translating a linear address to a physical address using TLB entries stored in a first TLB for fixed size pages, and translating a linear address to a physical address using fixed size TLB entries stored in a second TLB for variable size pages. In particular, the second TLB stores entries for variable size pages using fixed size TLB entries (e.g., fixed 4 M TLB entries for pages of sizes greater than 4 K and less than or equal to 4 M). Further, in this embodiment, the method includes OR""ing an upper offset of a linear address (e.g., bits 21:12 of a 32-bit linear address) with the lower corresponding number of bits of an entry in the second TLB (e.g., bits 9:0 of the physical page frame number) to generate the middle bits of a physical address (e.g., bits 21:12 of a 32-bit physical address) during the translation of the linear address to the physical address using the second TLB.
Other aspects and advantages of the present invention will become apparent from the following detailed description and accompanying drawings.